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| Number of Inputs: |
2 (synchronous) |
| Impedance: |
1MΩ or 50Ω
(75Ω available) Software Selectable |
| Coupling: |
AC or DC Software
Selectable |
| Analog Bandwidth: |
70 MHz (3 dB) |
| Resolution: |
12 Bits |
| Full Scale Input Range: |
±50mV, ±100mV,
±200mV, ±500mV, ±1V, ±2V, ±5V
Software Selectable |
| Absolute Max: |
±12 V |
| Common Mode Range: |
±3.5 V |
| CMRR: |
46 dB (at DC) |
| Gain Accuracy: |
+/- 0.1 dB relative to full scale (at 100 kHz) |
| Zero Accuracy: |
0.1% of range +/- 1mV (at DC) |
| DNL: |
< 1 LSB (monotonic) |
| INL: |
< 4 LSB |
| SNR: |
64 dB (500 kHz input,
1Vpp range) |
| SFDR: |
60 dB (1Vpp range) |
| Triggering: |
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| Source: |
Ch1, Ch2, Ext, S/W, Dig I/O |
| Levels: |
256 Steps |
| Slope: |
+ or – |
| External: |
±4V,100kΩ Zin,
50 ns
min Pulse width |
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| Sample Rate: |
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| Internal Clock: |
10 k to 40 MS/s (1 Hz
resolution) single channel
10k – 20 MS/s (1Hz resolution) dual channel
Software Selectable
Independent from output clk |
| External Clock: |
>=4x sample rate
input or output 100kΩ Zin, 80 MHz max |
| Memory: |
16 MB* local capture memory (shared with output memory) |
| PCI Interface: |
32 bit, 33 MHz Bus Mastering
(Continuous full speed capture of 2 chan at 20MSps per chan
(80 MB/s) to PC memory is supported) |
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| Number of I/O: |
16 (two 8-bit
ports), selectable as input or output |
| Input High: |
2.0 V, 5 V max |
| Input Low: |
0.8 V, 0 V min |
| Output High: |
2.4 V max @ 24 mA |
| Output Low: |
0.4 V min @ 24 mA |
| Power Up State: |
Input (High Impedance) |
| Counter/Timers: |
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| Number: |
2 (24 bits) |
| Clock: |
Internal from A/D or D/A clk |
| Speed: |
80 MHz Max |
| Modes: |
8254 modes 1, 2, 3, 5 |
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| Number of Outputs: |
2 (synchronous) |
| Impedance: |
50Ω (75Ω available) |
| Coupling: |
DC |
| Analog Filters: |
7th Order Butterworth, 8 MHz
3 dB Frequency |
| Resolution: |
12 Bits |
| Full Scale Output (into 50Ω load) Range: |
±50mV, ±100mV, ±200mV,
±500mV, ±1V, ±2V, ±5V Software Selectable |
| Gain Accuracy: |
+/- 0.1 dB relative to full scale (at 100 kHz) |
| Zero Accuracy: |
0.1% of range +/- 1mV (at DC) |
| DNL: |
< 1 LSB (monotonic) |
| INL: |
1 LSB |
| SNR: |
72 dB (500 kHz output,
1Vpp range) |
| SFDR: |
55 dB (1Vpp range) |
| Triggering: |
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| Source: |
Ch1, Ch2, Ext, S/W, Dig I/O |
| Levels: |
256 Steps |
| Slope: |
+ or – |
| External: |
±4V,100kΩ Zin,
50
ns min Pulse width |
| Sample Rate: |
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| Internal Clock: |
1Hz – 40MHz (1Hz resolution)
Software Selectable
Independent from input clk |
| External Clock: |
4x sample rate
input or output 100kΩ Zin, 80 MHz max |
| Memory: |
up to 16 MB* local waveform
memory |
| Operating Modes: |
Arbitrary Waveform with
Automatic looping Function (sine, square, triangle) |
| Sync Output: |
Software enabled
TTL compatible, 50Ω Zout 1 sample duration at
segment boundary |
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